A. Field of the Invention
This invention relates to data processing systems and more specifically to a distributed processing system for emulating multiple channels of a multichannel system having a single synchronous bus.
B. Background Art
Channel architectured systems perform input-output (I/O) data transfers between instruction processors (IP) and multiple peripheral devices by utilizing a dedicated I/O channel configuration. Coupled to each dedicated channel in the IP is at least one device controller, and each device controller is, in turn, coupled to at least one peripheral device. This I/O channel configuration permits the IP to communicate with several peripheral devices by way of the IP's multiple channel capability. The I/O channel configuration permits concurrent I/O data transfers on each channel. Each of these dedicated channels communicates with multiple device controllers, and each of the device controllers communicates with multiple peripheral devices.
In this I/O configuration, I/O instruction processing and channel management for each channel is primarily performed by the IP. This processing and managment is accomplished by the IP on a cycle stealing basis. Also, during a data transfer, a channel can operate in a burst mode. Burst mode operation dictates that once a multiple word data transfer begins on a channel, no other device controller can utilize that channel until the current data transfer has been completed.
In the channel architectured system I/O operations require extensive use of the IP. Other functions, such as data processing, cannot be performed while the IP is supporting channel operations.
Various channel architectured systems are known in the art. The principal channel architectured operating systems are DOS/VS, OS/VS1 and VM/370 of IBM. Such channel architectured systems require extensive hardware, consisting of an instruction processor having hardware channels, that require dedicated and costly controllers.
Therefore, it is an object of this invention to provide a high performance architecture which emulates a multichannel architecture but at a much lower cost by using distributed processors that communicate over a single synchronous system bus. These distributed processors are made up of microprocessor modules which perform the dual function of system bus controller and device controller.